CSE 141L: Introduction to Computer Architecture (Lab) (2024)

CSE141L - Winter 2022

Meets M/W from 12:00 to 12:50 in CENTR 115.

Pat Pannuto is the instructor, and their office is CSE 3202 (right in the corner).
Office hours Wednesday 3:30-4:20pm (via Zoom orin-person), or always available by appointment (please email / chat after class).

Overview

Hands-on digital design projects aiming to familiarize students with state machines, digital logic implementations, design of processor, control, and memory systems.This is a digital design, simulation, and synthesis project course.

This course is designed to run alongside CSE 141.We expect that you are enrolled in both.

Objectives

By the end of this course, students will be able to:

1. Learn correct hardware design practices suitable for FPGA and VLSI digital design.
2. Learn how to write Synthesizable Verilog, and to use the tools to turn it into a circuit.
3. Design, Implement, and Test your own digital circuits, all the way to an FPGA bitstream.
4. Learn about computer architecture in the best way – by doing.
5. Learn how programs and algorithms are implemented in hardware.
6. Work in a team, building a large, complex system using design principles that apply to both software and hardware.
7. Help your classmates and exercise your creativity.

Prerequisites

• CSE141 is a strongly enforced co-requisite. You must either be concurrently enrolled in CSE141 or have previously taken CSE141. It is expected that students take CSE141 and CSE141L in the same term.
• CSE140/140L (Required).This course assumes knowledges of circuits and primitives such as registers and gates, synchronous and combinational logic, state machines, and structures such as muxes and adders. We also assume some familiarity with tools (Quartus, ModelSim, and Verilog generally) from 140/140L.
• CSE110 (Strongly Recommended). 110 gives critical experience in the design, planning, and implementation of a large-scale project. It is strongly encouraged for students to take 110 first, as this course is also a large project but more of the planning and breakdown of work is your own responsibility in 141L.

Syllabus

DISCLAIMER

Due to our unusual circ*mstances, the details in this syllabus may change (e.g. schedule, grading policy, assignments, etc.). We will update this syllabus in the event of changes as the course progresses.

Instructor

• Pat Pannuto - ppannuto@eng.ucsd.edu

TAs

• Adithya Anand - ananand@ucsd.edu
• Link Lin - yul065@ucsd.edu
• Chavisa Thamjarat - cthamjar@ucsd.edu
• Kanlin Wang - kaw008@ucsd.edu

Schedule

Lectures are M/W from 12:00 to 12:50 US/Pacific, CENTR 115.

Expectations

Course format is two hours of lecture/demo/discussion per week, plusindependent work in the CSE basem*nt labs (B250, B260, B270) or at home on owncomputers. Attendance is strongly recommended, but not required, and alllectures are podcast.

Discussions, Q&A, peer-to-peer instruction, etc. take place on our Piazzawebsite. You are encouraged to post questions, help answer other students'questions, and provide feedback and suggestions to your instruction staff.

What is important to me is that students put forth an honest effort and treatone another, and the instructors, courteously and honestly. Constructivecriticism is always welcome.

Academic Integrity

This is a collaborative course, but students are expected to do their own workand to refrain from taking credit for the work of others.

Accommodations for Students with Disabilities

If you have a disability for which you are or may be requesting accommodations,please contactOffice for Students with Disabilities. Youmust have documentation from the Office before accommodations can be granted.

Assignments

Students shall work in teams of one to three members each.

Each group will work over the course of the quarter to design and implementa custom processor.

There are four reports, due at the starts of weeks 4, 6, and 8, plus the final report.Reports shall be submitted on Gradescope.

There is no final exam for this course. The complete processor and its finalreport are due at the end of the assigned "exam session."This quarter, that is 2:30pm US/Pacific on Wednesday, March 16.

Logistics

Submit reports on Gradescope.

We will use Piazza for Q&A.

Course Resources

• ModelSim (download or use on CSE B250/60/70 lab computers)
• Quartus Prime Lite (download or use on lab computers)

Grading

Each team shall design a specialized RISC processor.These will be tested on instructor-provided testbenches, and final coursegrades will depend on how well your designs perform against these testbenchesand whether your designs can be synthesized into actual digital gate-levellogic.

Milestones

There are intermediate deadlines (Milestones 1, 2, and 3).The primary goal of these is to help you ensure that you are on track.They will be evaluated by course staff, but this is primarily for feedback toyou for your benefit; generally these will not directly impact your finalgrade.

An imperfect milestone is okay, but take it as a very serious warningsign that you are behind; it will only get harder to catch up as timeprogresses.It is far better to submit what you have than to submit nothing.

Each incomplete milestone will lower your course grade by one notch (e.g. , A to A- or A- to B+).

Habitually late submissions may lower your course grade by one notch (e.g. , A to A- or A- to B+).

Agenda

This course meets for one hour twice a week.Loosely speaking, there will be one traditional lecture per week and oneinteractive demo session showcasing how to use tools or implement ideas coveredin lecture.

Update: In accordance with the campus policy, this course will be fullyremote for the first two weeks of instruction. We will meet on Zoom. See theCanvas announcement for more details.